Electronic Engineering MSc
MSc student in Electronic Engineering interested in computer architecture, RTL design, ASIC, FPGA-based acceleration, and hardware security. I care about how design choices at the electronic level shape performance, power, and security — from arithmetic units and FPGA pipelines to cache-timing side channels.
ETH Zurich — Switzerland
Master's Thesis Student
Designing a configurable multi-datatype arithmetic unit for ML workloads, extending the MXDOTP RISC-V ISA extension to support FP16 accumulation and mixed-datatype operations. Supervised by Danilo Cammarata, Gamze Islamoglu, and Prof. Dr. L. Benini.
EURECOM — Sophia Antipolis, France
MSc Internet of Things — Double Degree
Double-degree with Politecnico di Torino. Courses: System Security, Machine Learning and Intelligent Systems, Reinforcement Learning, Software Development. Semester project on cache-timing attacks against T-table AES on RISC-V hardware.
Politecnico di Torino — Italy
MSc Electronic Engineering — Embedded Systems
GPA 29.1/30. Courses: Computer Architectures, Microelectronic Systems, Integrated Systems Architecture, Synthesis and Optimization of Digital Systems, Operating Systems.
Politecnico di Torino / Tongji University
BSc Electronic Engineering — Double Degree
Final grade: 109/110. Double-degree with Tongji University, Shanghai. Final project: FPGA-based digital control of an agro-tech sensor using complex ASM.
EURECOM — France
Graduate Researcher
Research under Prof. R. Pacalet on hardware security and microarchitectural side-channel attacks on RISC-V. Developed and evaluated a cross-process L1 Prime+Probe attack against T-table AES on a BeagleV Fire / PolarFire SoC — cache-timing leakage, attacker-victim synchronization, noise characterization, and statistical key inference. Work accepted as a poster at RISC-V Summit Europe 2026.
Team RoboTO — Italy
Electronics Division Leader
Led the electronics division, coordinated a student team, managed deadlines, and developed supercapacitor modules for RMNA 2025 in San Diego (DJI Robomaster). Mentored junior members.
University of Perugia — Italy
Research Collaborator
Under Prof. S. Simonetti on biomechanical support systems. Designed and validated a back brace monitoring system using FSR sensors.
Politecnico di Torino — Italy
Teaching Assistant
TA for Computer Science (Python) course, A.Y. 2023/2024. Supported students during programming labs and algorithmic design activities.
Tongji University — China
Undergraduate Researcher
Supervised by Prof. X. Gong. Research on biological signal processing and EEG-based brain-computer interfaces for emotion recognition. Published at IEEE ICNC-FSKD 2024.
Multichannel Conv1D Hardware Accelerator
RTL accelerator for 1D convolution under strict resource constraints. Output-centric scheduling, tiling, Croc SoC integration, bare-metal C drivers, full RTL-to-GDSII flow. 149.5× CPU speedup. Verilator, Yosys, OpenROAD.
Low-Latency FPGA Pipeline for UDP Market-Data Processing
Zynq-based FPGA pipeline for MoldUDP64 / ITCH UDP market-data processing. Flat-FSM RTL parser for Ethernet, IPv4, UDP, MoldUDP64, and ITCH Trade messages, connected to a fixed-point decision engine. Deterministic packet parsing and hardware-accelerated decision logic. Verilog, Vivado, Vitis, AXI-Stream, AXI DMA, AXI-Lite, Zynq-7020.
Cache-Timing AES on RISC-V
Cross-process L1 Prime+Probe attack on T-table AES. BeagleV Fire / PolarFire SoC. Cache-set leakage analysis, attacker-victim sync, noise characterization, partial key recovery via statistical inference.
Pipelined DLX Processor
Fully pipelined DLX processor in RTL. Full instruction support, branch prediction, hazard management, and forwarding logic. Performance-oriented datapath/control design. VHDL, QuestaSim.
Multi-Vth Power Optimization
TCL-based low-power optimization flow: selective cell swapping to higher-Vth variants while preserving timing, with automated tuning and result aggregation in Synopsys PrimeTime.
Linux Scheduler Experiments
Automated benchmarking of Linux scheduling policies in a QEMU environment: kernel config, workload execution, tracing, latency analysis. Linux 5.4.281, QEMU, BusyBox, Ftrace, GCC.
PACMAN Embedded Game
Custom Pac-Man on LandTiger LPC1768. Real-time gameplay, joystick input, A* ghost pathfinding, chase/frightened FSM, scoring, sound effects. C, Keil µVision, ARM Cortex-M3.
Publications
RISC-V Summit Europe 2026 — Accepted Poster
From Leakage to Exploitability: Empirical Study of Cross-Process L1 Prime+Probe on RISC-V
IEEE ICNC-FSKD 2024
Phase-Amplitude Coupling of EEG Applied in Music-Induced Emotional Recognition Tasks
doi: 10.1109/ICNC-FSKD64080.2024.10702312 ↗Awards
Languages
Available for research collaboration and internship opportunities. The fastest route is email or LinkedIn.